What Is a PCIe Bandwidth Calculator?

A PCIe bandwidth calculator converts a generation and a link width into the throughput the link can actually deliver: raw signalling rate, the data rate after line encoding, the usable rate once transaction overhead is paid, and the IOPS ceiling for a given payload size and read/write mix. It is the difference between the number on the box — PCIe 5.0 x16 — and the number an application measures, which is why a card that looks starved on paper often turns out to be latency-bound rather than bandwidth-bound.

Both figures matter because they answer different questions. Bandwidth decides how long a large sequential transfer takes; IOPS decides how many small random accesses a device can sustain, and in most real workloads the second number is the one that limits performance.

How It Works

Each PCIe generation sets a signalling rate per lane — 2.5 GT/s for 1.0, 5 for 2.0, 8 for 3.0, 16 for 4.0, 32 for 5.0, 64 for 6.0 — and the link carries that rate on every lane in both directions simultaneously. The transfer rate is not the data rate: 8b/10b encoding on the first two generations spends 20% of the bits on ensuring DC balance and clock recovery, while the 128b/130b scheme from 3.0 onwards spends under 2%, and PCIe 6.0 replaces it with a 242/256 FLIT encoding. PCIe 4.0 x16 therefore carries 256 Gb/s of raw signalling but delivers about 252 Gb/s, or 31.5 GB/s, of decoded data per direction.

The transaction layer takes its own share. Every packet carries a 12 to 16 byte header plus up to 4 bytes of CRC, so a 256 byte payload spends roughly 11% of the link on framing while a 4,096 byte payload spends closer to 2%. That is why maximum payload size is worth configuring: moving from 128 to 512 bytes changes real throughput measurably on the same hardware.

IOPS then follows from latency rather than bandwidth. A 4 KiB random read needs a round trip of one to two microseconds before its data returns, so a single queue cannot exceed a few hundred thousand IOPS no matter how wide the link is. Once the queue is deep enough to cover the round trip, the link's bytes per second becomes the limit again — which is why enterprise drives use queues dozens deep and why the two ceilings have to be computed separately.

Understanding Your Results

The primary card is the data rate per direction at the selected generation and width. The three-stat bar sets the raw link rate, the usable throughput after overhead and the mixed-workload IOPS side by side.

The breakdown table walks from the per-lane signalling rate through encoding and transaction overhead to the effective rate, adds the legacy datasheet figure for that width, the read and write IOPS ceilings at your payload size and a comparison of every generation at the same link width, which is the quickest way to see what a generation upgrade buys. The summary panel repeats the headline numbers and prints the verdict line.

Two cautions on use. The model applies a fixed 11% transaction overhead, which matches a 256 to 512 byte payload well but overstates the cost for 4 KiB payloads and understates it for 128 byte ones; adjust your expectation rather than the model if your traffic differs. And real systems rarely achieve these figures end to end: chipset-attached slots share uplink bandwidth, switches add their own latency, and the host's memory bandwidth and software stack impose their own ceilings. Use the numbers as the link's capability, not as a promise about your application.