From GT/s to GB/s: What the Numbers Really Mean

PCIe bandwidth is quoted in gigatransfers per second per lane, and the arithmetic from there is multiplication and subtraction: per-lane rate times lane count gives the raw link rate, and subtracting the encoding overhead gives the usable data rate. A PCIe 4.0 x16 link therefore runs 256 Gb/s raw, 252.3 Gb/s after 128b/130b encoding, or 31.5 GB/s per direction. The headline '32 GB/s' figure is the per-direction rate. Summing both directions doubles it, but that aggregate number flatters workloads that mostly move data one way, and PCIe is genuinely full-duplex — both directions are available simultaneously.

Why the Encoding Overhead Skews the Generations

PCIe 1.x and 2.x use 8b/10b line encoding, which burns 20% of every byte in clock-recovery overhead. PCIe 3.0 and later switched to 128b/130b, cutting the waste to 1.54%, and PCIe 6.0 moved to PAM4 signalling with 242b/256b. This is why the 2.0-to-3.0 jump looked larger in practice than the raw numbers suggest: 5 GT/s at 8b/10b delivers 500 MB/s per lane while 8 GT/s at 128b/130b delivers about 985 MB/s — nearly doubling usable bandwidth for a 60% raw increase. Each generation doubles the per-lane transfer rate, and the encoding choice determines how much of that survives to the data layer.

The Gap Between Theoretical and Real Throughput

Every transaction-layer packet carries a header — 12 to 16 bytes — plus CRC in PCIe 3.0 and later, so real workloads land at 85 to 92% of the data rate even before the device controller adds its own overhead. The gap widens sharply with small transfers, where fixed per-packet costs consume a larger share of each transaction. This is also why a PCIe 4.0 NVMe drive in a PCIe 3.0 slot loses roughly half its sequential throughput while its random IOPS may barely change — random performance is usually limited by the drive's controller and NAND latency, not the link.

Bandwidth Versus IOPS: Picking the Honest Metric

For large sequential transfers, bandwidth is the metric that matters and the encoding math above gives a solid ceiling. For small random reads, latency dominates: a 4 KiB read takes a round trip regardless of link speed, so maximum IOPS is bounded by one transaction per round trip, not by gigabytes per second. The Professional Mode model here estimates read, write, and mixed IOPS from payload size and an assumed round trip, which is a better predictor of NVMe random-read performance than any bandwidth figure. As with all estimates, treat the output as a planning tool rather than a specification — controllers, drives, switches, and root complexes all add their own behaviour between the spec sheet and the benchmark.